This invention relates to semiconductor processing and, more particularly, to a novel process for improving the operation of silicon-on-sapphire devices by removing or minimizing edge current leakage.
Instabilities, such as excessive leakage current with zero applied gate voltage, has been a significant source of rejects in certain Silicon-On-Sapphire (SOS) Field Effect Transistors (FET's) since SOS/FET devices were first used in high density configurations. These instabilities were especially noticeable after the FET's were operated at temperatures in excess of about 150.degree. C. and, for the most part, this leakage appears most frequently in N-channel SOS/FET devices. Further, this excessive leakage manifested itself by premature "turn-on" in addition to the relatively high source-drain leakage currents.
In U.S. Pat. No. 3,890,632, STABILIZED SEMICONDUCTOR DEVICES AND METHOD OF MAKING SAME which issued to W. E. Ham et al. on June 17, 1975 and is assigned to the same assignee as the subject application there is described and claimed a novel stabilized semiconductor device and method which substantially overcomes the aforementioned disadvantages by introducing conductivity modifiers into selected edge regions of the channel region. In that patent, a mesa of single-crystal semiconductor device is formed on an insulating substrate such as sapphire. Since the silicon islands have traditionally been formed using an anisotropic etch, the resulting mesa or island will have side surfaces extending transversely from the substrate as well and a channel region that extends from one side surface to its corresponding opposite side. The invention therein teaches the selective doping of the edge regions of the channel region, adjacent the opposite side surfaces, in order to introduce more conductivity modifiers into the edge regions than the remainder of the channel region. The net result is a marked increase in threshold voltage levels in the doped regions which significantly reduces leakage current.